gcc - What do these Makefile constructs mean? -


Can someone help me to create that file? 

  BINS = file1 file2 file3 all: $ (BINS) clean: RM-F $ (BINS) * ~ $ *: $ @. CGCC-GO-$ @ $?

These are my questions:

  1. What is the G-C option?
  2. $ * and $ @
  3. How to know this to execute the final goal?

Thank you!

by GCC and create documentation:

  1. "- The creation of live debugging information is the basic form of operating system".

  3. a $ * that stem with which it matches an implicit rule (see how pattern matching). If target is DIR / AFUB and target pattern The stem dir / ef is useful for the creation of names of related files, in a static pattern rule, the stem file is part of the name that matches the '%' in the target pattern. "

    b "$ @", the target name of the file name if the target collection is a member, So the name '$ @' is the name of the archive file. In a pattern rule in which there are many goals (see Introduction to Pattern Rules), '$ @', the name of the target's rule is to run the rules. "

    c" $? "The names of all the essential things that are new to the target, are spaces between them." (Not asked, but worth adding.)

  4. "Compile the entire program. It should be the default goal."

This example makefile is a little limited, because it seems to create only C programs, there are many more comprehensive examples in it, to learn how to write macrophil Are useful.


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