hardware - How would you implement this digital logic in Verilog or VHDL? -

I have posted for which Verilog or VHDL requires some digital logic so that it is programmed in an FPGA To be.

How would you implement the following logic diagram in Verilog, VHDL, or any other hardware description language?

Numbered boxes represent bits in a field. The is bits in each field, and current and mask to bits by a computer system (using a Register or equivalent lying) will be given. The bits given in next will be read in the same computer system.

Also see:

Something like this ?

module scheduler # (parameter K = 10) (input wire [K: 1] current, input wire [K: 1] mask, output reg [K: 1] next); Reg [k: 1] A; Reg [k: 1] b; // '[i + 1]' buses that are wrapped // For example, a 4-bit bus ... // a [i]: one [4], one [3], one [2], one [1] (obviously ...) // a_wrap [i]: one [1], one [4], one [3], one [2] wire [K: 1] mask_vap = {mask [1], Mask [K: 2]}; Wire [ke: 1] a_wrap = {a [1], one [k: 2]}; Wire [ke: 1] current_use = {current [1], current [of: 2]}; Integer I; Always start with @ (*) (i = 1; i & lt; = K; i = i + 1) a [i] = ~ current_ speech [i] & amp; Amp; B [i]; B [ii] = one_ speech [ii] || Mask_wrap [i]; Next [i] = ~ a [i] & amp; Amp; Mask_wrap [i]; End End Module

(Disclaimer: linked but not simulated)