I posted this digital logic diagram as one. It describes a logic system that will be coded into Verilog or VHDL and will eventually be implemented in an FPGA.
The numbered boxes in the picture represent bits in a field. The is bits in each field, and current and mask to bits by a computer system (using a Register or equivalent lying) will be given. The bits in next will be read back in the same computer system.
I have posted the solution, as long as there is at least one bit set in the mask field, and the exact current bit field in a bit The idea is that the computer system will become the next bit field current bit field after doing some tasks (a scheduling operation in the original definition).
So, my question is: How do you modify this system so that it can handle the particular case where current bit fields all zeros (no bit set No) As it stands, if all the beats in current are zero, the output will also be zero, even if the bits are not set in the mask .
Ideally, if current is all zero, the lowest set bit in mask should be set to next . The system should still add more intense logic gates to any number of scalable (K). The spirit of the original question was to come up with a solution that would be straightforward to apply in any number.
Also see:
For me, I have users tell the FPGA that They should have one of the bits to enter 1.
However, if this is not your favorite solution, initially what is wrong in feeding all the current inputs in a large NOR gate (so that all is right input, only when the output is correct). All current lines of his and Fats already holds the current [1] or its entrance to continue with this exception or depart with the output of our note Gate
In this way, the current [1] If all the streams are wrong then it is correct to enter the door. Note
I understand Boolean algebra, but I've never worked on raw hardware - I think you indicated and the gate to ensure accurate time will need all the input buffer , But I suspect you would know better than me.
If left in the following diagram, then he fixes the code / previous block - the latest SO update has filled them (except for them proportional, fixed width, not fonts). Anyway, eJames' graphical diagram is better.
This is my diagram, slightly less elegant than yours: -):
+ ------- -------- ---- + | | | + ---- | Present [1] ----- + ------ \ \ | | NOR | O - + | Current [2-K] --- + ------ / / | | | + ---- | | | + \ / + | | \ _ / | + --- - | Or | \ / Buffer \ / + --- | | + --- + + --- + | 2-k | | 1 | & Lt; - These signal feed + + --- + + - in your end gates
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